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Security & Cryptography·DatasheetProduction Ready
AES (Advanced Encryption Standard)
AES-128/192/256 in clean, readable C⏚.
Overview
A hardware AES encryption / decryption core supporting all three key sizes, with a pipelined datapath tuned for FPGA resources. Written in readable C⏚ so you can audit and adapt it - not an opaque netlist.
Key features
- -AES-128 / 192 / 256
- -Pipelined datapath, optimized for FPGA resources
- -Encryption and decryption
- -Written in readable, auditable C⏚
Standards
- -FIPS 197 (AES)
Interfaces
| Data | 128-bit block in / out, streaming |
|---|---|
| Key | 128 / 192 / 256-bit key schedule |
| Mode | Block core (chain externally for CBC/CTR) |
Performance
| Block size | 128-bit |
|---|---|
| Throughput | Pipelined - available on request |
Resource utilization
| LUTs / logic cells | Available on request |
|---|---|
| Registers (FF) | Available on request |
| Block RAM | Available on request |
| Max clock (fMAX) | Available on request |
Verification
- -Validated against FIPS-197 test vectors
- -Encrypt/decrypt round-trip checked
Deliverables
- -C⏚ source (readable, modifiable)
- -Generated synthesizable Verilog (VHDL on request)
- -Self-checking testbench
- -Integration guide + this datasheet
- -Email integration support (per license tier)
Typical applications
- -Link / storage encryption
- -Secure boot & config
- -Defense / regulated systems
- -IoT data protection
Licensing
Single-project or perpetual; source-included for audit. Quoted per use.
Pricing is quoted per use (single project, perpetual, volume, support tier). Each license includes the full C⏚ source, generated HDL, a self-checking testbench, and integration support.
Neosyn · neosyn.io - Specifications subject to change. Resource and timing figures marked “available on request” are provided per target device on enquiry.