AES (Advanced Encryption Standard)
AES-128 / 192 / 256 encryption and decryption in clean, readable C⏚.
Overview
A hardware AES core supporting 128-, 192- and 256-bit keys, with the key size chosen at build time. Encryption and decryption datapaths, hardware key expansion, and an iterative round datapath tuned for FPGA resources. Verified against the FIPS-197 and NIST AESAVS known-answer vectors for all three key sizes, in both directions, on every build. Written in readable C⏚ so you can audit and adapt it - not an opaque netlist.
Key features
- -AES-128, AES-192 and AES-256, encrypt and decrypt (key size selected at build time)
- -FIPS-197 Appendix B + C.2 + C.3 known-answer tests both directions, plus NIST AESAVS GFSbox
- -Iterative round datapath, optimized for FPGA resources
- -Written in readable, auditable C⏚ - full source included
Standards
- -FIPS 197 (AES)
Interfaces
| Key | 128 / 192 / 256-bit key, as 32-bit words (high-order first) |
|---|---|
| Data | 128-bit block in / out, with valid handshake |
| Mode | Encrypt / decrypt block core (chain externally for CBC/CTR) |
Performance
| Block size | 128-bit |
|---|---|
| Throughput | Iterative - available on request |
Resource utilization
| LUTs / logic cells | Available on request |
|---|---|
| Registers (FF) | Available on request |
| Block RAM | Available on request |
| Max clock (fMAX) | Available on request |
Verification
- -Encryption and decryption validated against the FIPS-197 known-answer tests for all three key sizes (Appendix B, C.2, C.3)
- -Decryption KATs reuse the encryption vectors reversed, so the pair proves an encrypt/decrypt round trip
- -Encryption also validated against the seven NIST AESAVS GFSbox vectors for AES-128
- -All gated on every build, in Verilog simulation and the C⏚ simulator
Deliverables
- -C⏚ source (readable, modifiable)
- -Generated synthesizable Verilog (VHDL on request)
- -Self-checking testbench
- -Integration guide + this datasheet
- -Email integration support (per license tier)
Typical applications
- -Link / storage encryption
- -Secure boot & config
- -Defense / regulated systems
- -IoT data protection
Licensing
Single-project or perpetual; source-included for audit. Quoted per use.
Pricing is quoted per use (single project, perpetual, volume, support tier). Each license includes the full C⏚ source, generated HDL, a self-checking testbench, and integration support.
Neosyn · neosyn.io - Specifications subject to change. Resource and timing figures marked “available on request” are provided per target device on enquiry.