IP core catalog
FPGA IP cores in C⏚
Source-included IP, written in readable C⏚ and compiled to standard Verilog. Hardware-proven designs you can audit, modify, and integrate with confidence.
Networking
Complete Ethernet MAC layer implementation with auto-negotiation and MII/GMII support. FPGA-proven on Lattice ECP3 Versa board.
- -Full-duplex operation at 10/100/1000 Mbps
- -100% hardware operation (no processor needed)
- -Auto-negotiation with MII/GMII
From $4,000 · source included
Full UDP/IP protocol stack implementation for embedded networking applications. Hardware-only operation, no CPU required.
- -Full-duplex operation at 10/100/1000 Mbps
- -100% hardware operation (no processor needed)
- -FPGA-proven on Lattice ECP3 Versa with Marvell 88E1119R PHY
From $10,000 · source included
Security & Cryptography
Hardware implementation of AES-128/192/256 encryption and decryption, key size selected at build time, verified against the FIPS-197 and NIST AESAVS known-answer vectors for all three sizes in both directions. Written in C⏚ for clarity and maintainability.
- -AES-128, AES-192 and AES-256, encrypt and decrypt (key size selected at build time)
- -FIPS-197 (App B/C.2/C.3) both directions and NIST AESAVS GFSbox, gated on every build
- -Iterative round datapath, optimized for FPGA resources
From $3,000 · source included
Sample SHA-256 implementation demonstrating C⏚ optimization techniques. Includes three versions from basic to optimized.
- -Three implementations: basic, ROM-optimized, shift register
- -Written straight from the standard specification
- -Demonstrates C⏚ optimization workflow
From $2,000 · source included
DSP & Math
Q16.16 fixed-point division and runtime shifts as portable logic - no vendor divider primitive, no DSP block. Shipped in both a combinational and a ~40x smaller sequential form so you pick the area/latency trade-off.
- -Q16.16 division: combinational (1 result/cycle) or sequential (~40x smaller, ~48 cycles)
- -32-bit barrel shifter - SLL/SRL/SRA by a runtime amount
- -No DSP blocks or vendor primitives - synthesizes on any FPGA
From $1,000 · source included
Processors
A 32-bit RISC-V CPU - RV32I base ISA plus the M extension (multiply/divide), with Zicsr and Zifencei. Single-cycle, loadable-program, written in readable C⏚.
- -RV32I + M extension (MUL/MULH*/DIV*/REM*), Zicsr & Zifencei
- -Single-cycle; loadable program over a boot stream
- -Runs a 10-program library (sort, recursive Fibonacci, matmul, …)
From $8,000 · source included
Partial implementation of the Intel 8088 processor in C⏚. Ideal for retrogaming and educational applications.
- -Partial 8088 instruction set
- -Designed for retrogaming applications
- -Educational tool for processor design
From $1,000 · source included
Licensing & custom development
Every core is licensed with full C⏚ source - single-project or perpetual, quoted per use (project, volume, support tier). Each license includes the source, generated HDL, a self-checking testbench, and integration support. Need a modification or a bespoke core (a custom protocol engine, accelerator, or interface)? We build IP in C⏚ to your specification.