IP Cores

FPGA-proven IP cores written in C⏚. Real designs, validated on hardware, with readable source code you can actually understand and maintain.

Why Choose Our IP Cores?

Written in C⏚, not Verilog. That means the source code is readable, maintainable, and easy to customize. No more deciphering cryptic HDL—see exactly what the hardware does.

FPGA-proven designs. Our networking cores have been validated on Lattice ECP3 Versa boards with real PHYs. These aren't simulation-only designs.

Transparent compilation. Unlike HLS black boxes, you can review the generated Verilog/VHDL. Understand what you're getting, optimize if needed, and integrate confidently into your design flow.

Networking

Ethernet MAC

FPGA-Proven

Complete Ethernet MAC layer implementation with auto-negotiation and MII/GMII support. FPGA-proven on Lattice ECP3 Versa board.

Features:

✓Full-duplex operation at 10/100/1000 Mbps
✓100% hardware operation (no processor needed)
✓Auto-negotiation with MII/GMII
✓FPGA-proven on Lattice ECP3 Versa with Marvell 88E1119R PHY
✓2KB receive buffer with frame filtering
✓Filters bad frames (no preamble, length errors, bad CRC)

Implementation: cg

UDP/IP Stack

FPGA-Proven

Full UDP/IP protocol stack implementation for embedded networking applications. Hardware-only operation, no CPU required.

Features:

✓Full-duplex operation at 10/100/1000 Mbps
✓100% hardware operation (no processor needed)
✓FPGA-proven on Lattice ECP3 Versa with Marvell 88E1119R PHY
✓2KB receive buffer with frame filtering
✓Filters bad frames (no preamble, length errors, bad CRC)

Implementation: cg

Security & Cryptography

AES (Advanced Encryption Standard)

Production Ready

Hardware implementation of AES encryption/decryption. Written in C⏚ for clarity and maintainability.

Features:

✓AES-128/192/256 support
✓Optimized for FPGA resources
✓Pipelined architecture
✓Written in readable C⏚ code

Implementation: cg

SHA-256

Production Ready

Sample SHA-256 implementation demonstrating C⏚ optimization techniques. Includes three versions from basic to optimized.

Features:

✓Three implementations: basic, ROM-optimized, shift register
✓Written straight from the standard specification
✓Demonstrates C⏚ optimization workflow
✓4x size reduction from basic to optimized
✓Fewer muxes and simpler logic in optimized version

Implementation: cg

Processors & Retro Computing

Intel 8088

Available

Partial implementation of the Intel 8088 processor in C⏚. Ideal for retrogaming and educational applications.

Features:

✓Partial 8088 instruction set
✓Designed for retrogaming applications
✓Educational tool for processor design
✓Written in readable C⏚ code

Implementation: cg

Licensing & Support

All IP cores are available for licensing with full source code access. Choose between perpetual licenses or subscription-based models.

What you get: Complete C⏚ source code, generated Verilog/VHDL, testbenches, documentation, and technical support during integration.

Custom development available. Need modifications or a completely custom IP core? Our team can develop bespoke solutions written in C⏚ to your specifications.

Need a Custom IP Core?

We design custom IP cores in C⏚ tailored to your exact requirements. Whether you need a specialized protocol engine, a custom accelerator, or a unique interface—we can help.

Readable

C⏚ source you can understand and maintain

Validated

Tested on real FPGA hardware

Transparent

Review generated HDL before deployment

Discuss Your Project