The first FPGA languagebuilt for AI.
A C-like hardware language that compiles to clean, standard Verilog - with an MCP agent toolkit and a 10x simulator, built for engineers and the AI agents working alongside them.
14-day free trial · no credit card · runs on any FPGA
Proven in production
Neosyn is the next chapter of a toolchain with real silicon behind it. Shipped as Synflow, this technology - the compiler and the IP cores - went into production at:
- and with dozens of startups and independent FPGA engineers across Europe and the US.
The proven core, rebuilt for the age of AI.
From C⏚ to silicon - and an agent doing it for you
Write a task, simulate it in the editor, generate Verilog, and watch the cg-agent-kit drive the same loop. The whole thing in under a minute.
14-day free trial · No credit card
Why C⏚ beats traditional HDL
Same silicon. Half the code. Built so an LLM can write it with you.
Traditional HDL (Verilog/VHDL)
Designed in the 1980s for a different era
- Verbose syntax
100+ lines for simple state machines
- Manual state management
Write your own FSMs, counters, protocols
- Slow simulation
Wait hours for large designs to simulate
- Vendor-specific tools
Locked into Intel, Xilinx, or Lattice ecosystems
- Opaque to AI
Cryptic errors and 1980s tooling - LLMs hallucinate Verilog they can't verify
C⏚ + Neosyn SDK
Hardware development for the age of AI
- C-like syntax
50% less code. Reads like software. Compiles to HDL.
- Built-in abstractions
Tasks, typed ports, and stream handshakes handle the hard parts
- 10x faster simulation
Cycle-accurate, high-speed simulator included
- Open & vendor-agnostic
One codebase, any FPGA - Intel, Xilinx, Lattice, Microchip, or a fully open-source flow (Yosys, nextpnr, Icarus)
- AI-native toolchain
An MCP server and a VS Code language server - self-checking examples and errors an LLM can actually fix
Built for the agents writing hardware now
LLMs hallucinate Verilog they can't verify. C⏚ closes the loop: agents drive the real compiler, work from validated code, and get errors they can actually fix.
MCP-native toolkit
The cg-agent-kit exposes the compiler, simulator, and synthesis check as MCP tools - agents drive the exact toolchain you do, not a guess at it.
Validated-code dictionary
Agents seed from a library of verified C⏚ that compiles and simulates - adapt-from-known, not invent-from-scratch. Fewer hallucinations, working hardware.
Errors an LLM can fix
Diagnostics name the cause and the fix - a width mismatch or an unsynthesizable construct comes back as a clear instruction, not a cryptic HDL trace.
A loop fast enough to iterate
The 10× simulator gives agents a compile→sim feedback loop tight enough to actually converge - write, run, read the result, repeat.
Three tools. One vision.
Hardware shouldn't be harder than software. We're building the complete stack for modern FPGA development-from language to silicon.
VS Code + MCP
Neosyn SDK
A VS Code extension: compile, simulate, and generate HDL for any FPGA vendor - plus an MCP server so AI agents drive the same toolchain. One workflow, no vendor lock-in.
Vendor Agnostic
Intel, Xilinx, Lattice, Microchip - or a fully open-source flow. Your code, any FPGA.
10x Faster Development
High-speed simulation. Readable code. Less debugging time.
Open Toolchain
Plugs into the open-source flow - Yosys synthesis, Icarus/Verilator sim, nextpnr. Standard Verilog out, no black boxes.
Open & vendor-neutral
Compiles to standard Verilog - no black boxes, no lock-in
An Ethernet MAC validated on a Lattice ECP3 with a real PHY, plus RISC-V and Intel 8088 CPUs - written in C⏚.
The C⏚ language server and the IP-core library are open - read the compiler, build it, run it against the open FPGA flow.
The same C⏚ synthesizes on Intel, Xilinx, Lattice, and Microchip - or end-to-end on Yosys + nextpnr.
CONTACT US
Let's talk about your needs, we'd love to hear from you!
Our Location
Startup Lisboa, Rua da Prata 80, 1100-420 Lisboa, Portugal
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