Fixed-Point Divider & Barrel Shifter
Q16.16 division and runtime shifts - the area/latency trade-off, both ways.
Overview
The integer-math building blocks an FPGA datapath needs when a plain `/` is not an option: a fixed-point Q16.16 divider in two flavours - a fully combinational one that returns a quotient every cycle, and a sequential one that is roughly 40x smaller for about 48x the latency - plus a 32-bit barrel shifter that shifts by a runtime amount (SLL / SRL / SRA). Every block is pure portable logic: no vendor divider primitive, no DSP block required, so it synthesizes on any FPGA. Known-answer tested on both backends on every build.
Key features
- -Q16.16 fixed-point division, q = (a << 16) / b
- -Two implementations from one algorithm: combinational (1 result/cycle) and sequential (~40x smaller)
- -32-bit barrel shifter - SLL / SRL / SRA by a runtime amount, one result per cycle
- -No vendor primitives and no DSP blocks - synthesizes on any FPGA, including DSP-less parts
- -Known-answer gated on every build, in both Verilog simulation and the C⏚ simulator
- -Readable, modifiable C⏚ source - retarget the word width or fixed-point format yourself
Standards
- -Q16.16 fixed-point arithmetic
- -Restoring long division
- -SLL / SRL / SRA shift semantics
Interfaces
| Divider in | a, b - 32-bit, streaming with handshake |
|---|---|
| Divider out | q - 32-bit Q16.16 quotient |
| Shifter | val + amt[4:0] + op (0=SLL, 1=SRL, 2=SRA) |
| Flow control | Push handshake; the sequential divider back-pressures its producer |
Performance
| Divide (combinational) | 1 result / cycle, ~10,050 LUTs + 33 FF |
|---|---|
| SeqDiv (sequential) | ~48 cycles / result, ~243 LUTs + 198 FF |
| BarrelShift | 1 result / cycle, ~229 LUTs + 33 FF |
| Operand range | Non-negative magnitudes (32-bit) |
Resource utilization
| LUTs / logic cells | Divide ~10,050 · SeqDiv ~243 · BarrelShift ~229 |
|---|---|
| Registers (FF) | Divide 33 · SeqDiv 198 · BarrelShift 33 |
| Block RAM | None |
| DSP blocks | None - portable to DSP-less devices |
| Max clock (fMAX) | Available on request |
Verification
- -Q16.16 known-answer tests on the combinational divider (7/7) and the sequential divider (7/7)
- -SLL / SRL / SRA known-answer tests on the barrel shifter (8/8)
- -Every test run on BOTH backends - cycle-accurate Verilog simulation and the C⏚ simulator - on every build
- -KAT vectors computed independently of the hardware (see tools/divider_kat.py)
Deliverables
- -C⏚ source (readable, modifiable)
- -Generated synthesizable Verilog (VHDL on request)
- -Self-checking testbench
- -Integration guide + this datasheet
- -Email integration support (per license tier)
Typical applications
- -Fixed-point DSP and control loops (PID, scaling, normalization)
- -Sensor linearization and unit conversion
- -Variable shifts in a CPU/ALU datapath
- -Any datapath on an FPGA without a hardware divider
Licensing
Single-project or perpetual; source-included so you can retarget the width or fixed-point format. Quoted per use.
Pricing is quoted per use (single project, perpetual, volume, support tier). Each license includes the full C⏚ source, generated HDL, a self-checking testbench, and integration support.
Neosyn · neosyn.io - Specifications subject to change. Resource and timing figures marked “available on request” are provided per target device on enquiry.