RISC-V (RV32IM)
A clean RV32IM single-cycle CPU in readable C⏚.
Overview
A 32-bit RISC-V processor implementing the RV32I base integer ISA plus the M extension (multiply / divide / remainder), with Zicsr and Zifencei. A single-cycle datapath with a loadable program - one core boots and runs any program over a count-prefixed instruction stream, so you are not locked to a baked-in ROM. Exercised against a library of real programs (bubble sort, recursive Fibonacci on a stack, memcpy, strlen, Euclid GCD, bitwise CRC-8, mul/div, a 3×3 matrix multiply, and a self-test). Readable C⏚ source you can audit and extend with custom instructions - and the same core that gates every Neosyn compiler release.
Key features
- -RV32I base integer ISA + M extension (MUL / MULH* / DIV* / REM*)
- -Zicsr (CSR) and Zifencei (FENCE.I) - non-trapping
- -Single-cycle datapath; Harvard instruction + data memory
- -Loadable program over a boot stream - one core runs any program
- -Sub-word loads / stores (LB/LH/LW · SB/SH/SW)
- -Readable, auditable, extensible C⏚ source
Standards
- -RISC-V Unprivileged ISA - RV32I
- -"M" standard extension (RV32IM)
- -Zicsr, Zifencei
Interfaces
| Program load | Count-prefixed boot stream (in) |
|---|---|
| Observation | Store address / data pulse (out) |
| Memory | Word-addressed instruction + data RAM |
| Halt | ECALL / EBREAK |
Performance
| ISA | RV32IM + Zicsr / Zifencei |
|---|---|
| Pipeline | Single-cycle (1 instruction / clock) |
| Max clock (fMAX) | Available on request |
Resource utilization
| LUTs / logic cells | Available on request |
|---|---|
| Registers (FF) | Available on request |
| Block RAM | Available on request |
| Max clock (fMAX) | Available on request |
Verification
- -Bottom-up tier gate - 13/13 atoms green on bytecode sim + Verilog (iverilog) elaboration
- -Runs a 10-program library end to end (sort, recursive Fibonacci, memcpy, strlen, GCD, CRC-8, mul/div, 3×3 matmul, self-test, FENCE/CSR)
- -Gates every Neosyn compiler release - continuously re-verified
Deliverables
- -C⏚ source (readable, modifiable)
- -Generated synthesizable Verilog (VHDL on request)
- -Self-checking testbench
- -Integration guide + this datasheet
- -Email integration support (per license tier)
Typical applications
- -Soft CPU / control processor in an SoC
- -Programmable sequencers & accelerators
- -A clean RISC-V base to extend with custom instructions
- -Processor-design education & bring-up reference
Licensing
Single-project or perpetual; source-included - a clean base to extend with custom instructions. Quoted per use.
Pricing is quoted per use (single project, perpetual, volume, support tier). Each license includes the full C⏚ source, generated HDL, a self-checking testbench, and integration support.
Neosyn · neosyn.io - Specifications subject to change. Resource and timing figures marked “available on request” are provided per target device on enquiry.