NeosynNeosyn

Neosyn SDK

The FPGA toolchain, in the editor you already use

Write C⏚, simulate 10× faster, and generate standard Verilog - all inside VS Code, with an MCP server so AI agents drive the same compiler you do.

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VS Code·cg-agent-kit (MCP)·10× simulator·Intel / Xilinx / Lattice / Microchip / Yosys

The value

Hardware development, brought up to date

FPGA tooling hasn't changed since the 1980s. C⏚ brings the readability, type safety and speed software has had for decades - without giving up control of the hardware.

Ship in half the code

C-like syntax with hardware semantics. The compiler builds the FSMs, counters, and valid/ready handshakes you'd otherwise hand-wire - so a stream filter is a dozen lines, not a hundred.

Catch bugs before silicon

Bit-accurate types flag width and sign errors live in the editor, and the cycle-accurate simulator gives a pass/fail in seconds - not after an overnight HDL sim or a board bring-up.

Own your whole stack

C⏚ compiles to clean, standard Verilog you can read and review - drop it into any vendor flow or the open-source flow. No encrypted netlists, no proprietary dongles, no lock-in.

Built for AI agents

The cg-agent-kit exposes the compiler, simulator, and synthesis check as MCP tools, so an agent writes C⏚, verifies it against the real compiler, and self-corrects - hardware an LLM can actually get right.

How it feels

One tight loop, all in the editor

Write a task, simulate it, generate Verilog - and watch an AI agent run the same loop. Each iteration is seconds, fast enough to actually stay in flow.

The same loop, step by step:

moving_avg.cgC⏚ source
// 4-tap moving-average filter - one sample per clock.
task MovingAvg {
  in  stream u8 sample;     // samples in
  out stream u8 filtered;   // smoothed out

  u8 window[4];             // sliding window
  u2 head;

  void loop() {
    u8 x = sample.read;
    window[head] = x;
    head = (u2)(head + 1);

    u10 sum = (u10)(window[0] + window[1]
                  + window[2] + window[3]);
    filtered.write((u8)(sum >> 2));
  }
}
1
Write. Clean C⏚ - the compiler builds the FSM, the window register, and the back-pressure for you.
2
Simulate. Fast Sim runs a self-checking test in seconds, right in the editor.
3
Generate. Emit standard Verilog (or VHDL) - readable, synthesizable, vendor-neutral.
4
Deploy. Into Vivado, Quartus, Libero, Diamond, or the open Yosys flow.
See the C⏚ language →

The toolchain

Four tools, one compiler

Compiler, simulator, editor and IP library - all sharing the same compiler your AI agents drive. Click any screenshot to enlarge.

VS Code extension

The toolchain lives in the editor you already use - completion, go-to-definition, hover docs, live type-safety diagnostics, plus FSM and netlist views and an MCP server for AI agents.

C⏚ → HDL compiler

Write in C⏚, compile to production-ready Verilog that synthesizes efficiently. No hand-editing, no vendor-specific quirks - clean, portable, reviewable RTL.

High-speed simulator

Cycle-accurate simulation at roughly 10× traditional HDL speed. Self-checking tests give a pass/fail in seconds - no VCD spelunking, no waveform archaeology.

IP core libraries

Real cores in C⏚ - a RISC-V CPU, the Intel 8088, a UART, an Ethernet MAC. Source-included blocks you can read, modify, and audit instead of opaque netlists.

A full language server, not a syntax highlighter

Everything you expect from a modern editor - for hardware.

✓Code completion & snippets
✓Go-to-definition & references
✓Hover documentation
✓Live type-safety diagnostics
✓FSM (state-machine) view
✓Netlist / graph view
✓Verilog & VHDL generation
✓MCP server for AI agents

Why trust it

Proven, open, and yours to keep

Real silicon behind the IP, a commercial track record you can check, and standard HDL out - so nothing about your design is locked to us.

Silicon-proven

An Ethernet MAC validated on a Lattice ECP3 with a real PHY, plus RISC-V and Intel 8088 CPUs - the IP library ships in C⏚ source.

A proven team

As Synflow, this technology went into production at Samsung, Thales, BAE Systems, DP Control and dozens of startups. Rebuilt for the age of AI.

Open toolchain

Standard Verilog/VHDL out, runs end-to-end on the open-source flow - Yosys, nextpnr, Icarus, Verilator. No black boxes.

Transparent, not a black box

This isn't High-Level Synthesis. C⏚ compiles to clean Verilog at the right level of abstraction - RTL you can read, review, and hand-tweak, then drop into any vendor flow or the open-source flow. You always know what you're getting.

Getting started

Runs where you already work

The SDK is a VS Code extension with the Java runtime bundled - install it and start writing C⏚ in minutes.

Windows

Windows 10 / 11
8 GB RAM · 2 GB disk
VS Code 1.85+

macOS

macOS 11+
8 GB RAM · 2 GB disk
VS Code 1.85+

Linux

Ubuntu 20.04+
8 GB RAM · 2 GB disk
VS Code 1.85+

Start building today

14-day free trial - full SDK access, complete documentation, and example projects. No credit card.

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