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Networking·DatasheetFPGA-Proven

UDP/IP Stack

Full UDP/IP in hardware - pairs with the Ethernet MAC.

Overview

A hardware UDP/IP protocol stack for embedded networking with no soft CPU. Sits on top of the Ethernet MAC to give you addressed datagram send/receive at line rate. Proven on the same Lattice ECP3 Versa platform.

Key features

  • -Full-duplex operation at 10 / 100 / 1000 Mbps
  • -100% hardware operation - no processor needed
  • -FPGA-proven on Lattice ECP3 Versa with a Marvell 88E1119R PHY
  • -2 KB receive buffer with frame filtering
  • -Drops malformed frames (no preamble, length errors, bad CRC)

Standards

  • -IPv4
  • -UDP (RFC 768)
  • -IEEE 802.3 below (via the Ethernet MAC)

Interfaces

Network sideEthernet MAC (MII/GMII PHY)
Application sideUDP datagram in/out, streaming
AddressingConfigurable IP / port

Performance

Line rate10 / 100 / 1000 Mbps, full-duplex
ThroughputWire-speed datagrams

Resource utilization

LUTs / logic cellsAvailable on request
Registers (FF)Available on request
Block RAMAvailable on request
Max clock (fMAX)Available on request

Verification

  • -Hardware-validated on Lattice ECP3 Versa with a Marvell 88E1119R PHY
  • -Datagram send/receive against standard hosts

Deliverables

  • -C⏚ source (readable, modifiable)
  • -Generated synthesizable Verilog (VHDL on request)
  • -Self-checking testbench
  • -Integration guide + this datasheet
  • -Email integration support (per license tier)

Typical applications

  • -Telemetry / data streaming
  • -Sensor & DAQ uplinks
  • -Machine-to-machine links
  • -Low-latency control

Licensing

Single-project or perpetual; bundles well with the Ethernet MAC. Quoted per use.

Pricing is quoted per use (single project, perpetual, volume, support tier). Each license includes the full C⏚ source, generated HDL, a self-checking testbench, and integration support.

Neosyn · neosyn.io - Specifications subject to change. Resource and timing figures marked “available on request” are provided per target device on enquiry.