Open source
Your hardware should never depend on us staying in business
The C⏚ Verilog compiler is open source under the Mozilla Public License 2.0. Build it yourself, fork it, audit it - and if Neosyn ever disappears, your designs keep compiling forever. That's a promise we put in a license, not just a sentence.
Why we're doing this
The question every serious user asks first
“What happens to my chips if your company stops?” It's the right question - silicon outlives startups. For years the only honest answer was “trust us.” Now the answer is a public repository under an OSI-approved license: github.com/Neosyn-Logic/cg-compiler.
When this technology was Synflow, customers shipped real products on it - and every one of them eventually asked the same thing. An open compiler is the only answer that survives a bad year, an acquisition, or a founder walking away.
So the engine that turns C⏚ into Verilog will be yours as much as ours. No escrow clause to invoke, no source-code-on-bankruptcy negotiation. The code is just there, in the open, today and after we're gone.
Open core, honestly
What's open, and what keeps the lights on
We're not pretending everything is free. The compiler - the part you'd need to never be locked in - is open: build it from source and it just works. You pay for ease of use and premium features - the supported prebuilt extension, the fast simulator, the IP cores - never for permission to compile.
Open - MPL-2.0
The C⏚ language
Grammar, type system and validation - the full frontend.
The Verilog compiler
C⏚ → clean, standard Verilog. The complete generation path.
The editor integration
The LSP server: live diagnostics, hover, navigation.
The runtime library
The bundled Verilog primitives your designs are built on.
Commercial
The supported prebuilt extension
The ready-to-install, activated VS Code build - convenience and support, packaged. Or compile from source for free.
The fast simulator
Cycle-accurate simulation in seconds, no HDL toolchain. Our headline feature.
The IP cores
Production-proven Ethernet, AES, RISC-V and more. This is how we pay the bills.
Premium support
SLAs, integration help, and engineering time on your project.
The fast simulator and VHDL output are not part of the open compiler today. The open project targets standard Verilog - the universal, vendor-neutral output every FPGA and ASIC flow accepts.
The promise
In plain terms
No legalese games. Here is exactly what the license guarantees you.
Build it yourself
Clone, compile, run. The Verilog compiler works with no license key and no account - free, forever.
Fork it if you must
MPL-2.0 means you can fork and keep it alive on your own terms. Improvements to the files flow back to the community.
No lock-in
Output is clean, standard Verilog you can read, review and drop into any flow. Walk away whenever you want - with your designs.
The full source is on GitHub at github.com/Neosyn-Logic/cg-compiler. Clone it, build it, and compile C⏚ to Verilog yourself.
An open compiler, a serious toolchain
Start designing in C⏚ today - the fast simulator, the IP cores and the support are all here when you need them.