Get C⏚
Three ways in: the VS Code extension for humans, the MCP server for AI agents, and the compiler source for anyone who wants to own their toolchain. They all drive the same compiler.
VS Code extension
The full toolchain in the editor you already use: compiler, Fast Sim, Verilog and VHDL generation, FSM and netlist views.
- ✓ Compile C⏚ → portable Verilog
- ✓ Cycle-accurate Fast Sim, no waveform spelunking
- ✓ Intel, Xilinx, Lattice, Microchip, or a fully open-source flow
Needs a license - 14-day trial, no card.
Or install straight from your editor. Search Neosyn C⎕ in the Extensions view - VS Code and Open VSX (VSCodium, Cursor, Windsurf) both carry it. Free to install, no account; it asks for a license the first time you open a .cg file.
cg-agent-kit
A separate MCP server that hands the compiler, simulator and synthesis check to Claude, Cursor, Windsurf - any MCP client. The agent verifies its own hardware.
- ✓ Compile, simulate and synth-check as MCP tools
- ✓ 28 worked examples and a validated-code dictionary
- ✓ Works against the open-source jar - no license required
Open source · PyPI
Compiler source
The C⏚ frontend, the Verilog generator and the language server are open source. Build it, read it, fork it - your designs keep compiling even if we disappear.
- ✓ C⏚ → standard Verilog, no license gate
- ✓ Runs the open flow: Yosys, nextpnr, Icarus
- ✓ No VHDL, no Fast Sim - those are commercial
Read the open-core promise.
What the license actually buys
You never pay for permission to compile - the Verilog path is open source and always will be. You pay for the parts that save you a day: simulation without an HDL toolchain, VHDL, the views, and a build that just works.
Write C⏚ — syntax highlighting, snippets, file icons
Ships in the extension, no license needed
Live diagnostics, hover, go-to-definition, inlay hints
Language server — starts only with a valid license or trial
Compile C⏚ → standard Verilog
Open source (MPL-2.0) — build the compiler yourself, forever
Fast Sim — cycle-accurate simulation in seconds, no HDL toolchain
The headline feature. Nothing to install, no waveform spelunking
VHDL output
Verilog is the open path; VHDL is commercial
FSM and Graph views — see what actually synthesizes
Renders the compiled design, not your source
Production IP cores — Ethernet, AES, RISC-V, UART, 8088
Datasheets and pricing on the IP cores page
Prebuilt, signed, supported extension + updates
Or compile from source for free and support yourself
The license is bound to one machine and checked before the language server starts. Without it you still get syntax highlighting and snippets; everything driven by the compiler waits. Start a 14-day trial - three fields, no credit card.
Before you install
- Java 17 or newer on your PATH. The compiler runs on the JVM and the extension does not bundle a runtime. Check with
java -version; if it is missing, get Eclipse Temurin 17 - free, all platforms. - VS Code 1.85+ on Windows 10/11, macOS 11+, or Linux. 8 GB RAM, 2 GB disk.
- cg-agent-kit needs Python 3.10+ and a compiler jar - see the setup guide.
Step-by-step instructions live in the install guide.