Install
Two ways to get C⏚ on your machine. The VS Code extension is the supported editor surface; the standalone JAR is for CI, headless scripting, and editor integrations of your own.
Both are built around the same language-server JAR and the same core compiler pipeline. Packaging differs; the language and generated outputs match for the same tool version.
Requirements
- VS Code extension: VS Code plus Java 17 or newer on
PATH. - Standalone JAR / CLI: Java 17 or newer on
PATH.
Project layout
The compiler expects package names, file names, and folder paths to agree:
- A file declaring
package com.example;should live under<src-root>/com/example/. - The file base name should match the top-level entity it defines.
Example:
task Counternormally lives inCounter.cg. - Imports use the fully-qualified entity name, such as
import com.example.Counter;.
Minimal example:
my-project/
src/
com/
example/
Counter.cg
Counter_test.cgIf you skip this layout, imports and top-level entity discovery may fail even when the code itself is valid.
See Project layout for the stricter rules, recommended repository shape, and common failure modes.
VS Code extension
The fastest setup. The extension bundles its own
cg-language-server.jar, so the main external requirement is a
Java 17 or newer runtime on PATH.
From the marketplace
code --install-extension neosyn.neosyn-cgOr search Neosyn C⏚ Language in the Extensions view (publisher:
neosyn, extension ID neosyn-cg) and click Install.
From a .vsix file
If you need a specific version, download the .vsix from the
releases page
and sideload it:
code --install-extension neosyn-cg-X.Y.Z.vsixReload the VS Code window (Developer: Reload Window from the
command palette) so the language server picks up.
Verify
Open any .cg file (or paste the snippet from the
Quick tutorial. You should see syntax
highlighting and a Neosyn: Fast Simulation (Bytecode) play-icon
in the editor title bar. Run it: if the bytecode simulator
prints to the Output → Neosyn C⏚ channel, the install is good.
Standalone CLI
The language-server JAR runs as a long-lived LSP server (for editor integrations) and as a one-shot CLI (for scripting and CI). The CLI is the most direct way to drive the compiler and is the best reference surface when you need explicit flags and reproducible commands.
See CLI reference for the command-oriented version of this section.
Get the JAR
Download cg-language-server.jar from the
releases page,
or grab it from a VS Code install:
ls ~/.vscode/extensions/neosyn.neosyn-cg-*/server/cg-language-server.jarTo build from source:
git clone https://github.com/Neosyn-Logic/neosyn-studio.git
cd neosyn-studio/releng/lsp-server
mvn clean package -DskipTests
# → target/cg-language-server.jarMaven 3.9 or newer is required (Tycho dependency).
Sanity check
java -jar cg-language-server.jar --versionThis should print a version string. If you get
UnsupportedClassVersionError, your java is too old. Run
java -version and upgrade to 17 LTS or newer.
CLI surface
| Command | Alias | Purpose |
|---|---|---|
simulate | sim | Run the bytecode simulator on a .cg file |
generate | gen | Emit synthesizable Verilog or VHDL |
generate-ir | ir | Dump the internal IR (XMI) for inspection |
Common flags: --entity <name> selects the top-level entity when
there is more than one in scope. --target verilog|vhdl switches
the HDL backend (default Verilog). --output <dir> overrides
the output directory. --help and --version work everywhere.
Defaults worth knowing:
simulatewrites a VCD by default.simulatestops at the tool's default cycle cap unless the test terminates earlier.generatewrites toverilog-gen/orvhdl-gen/unless--outputis supplied.
A typical end-to-end invocation:
java -jar cg-language-server.jar simulate Counter_test.cg
java -jar cg-language-server.jar generate Counter.cg --target verilogThe first runs the cycle-accurate sim and, by default, writes a VCD
at the project root (named after the top-level entity). The second
emits Verilog under verilog-gen/ at the project root, preserving
the source's package path.
Next
Walk through the Quick tutorial to write your first counter, simulate it, and generate Verilog. About ten minutes end to end.