CLI reference

The cg-language-server.jar executable runs in two modes:

• LSP mode with no subcommand
• CLI mode with a single subcommand such as simulate

Requirements

• Java 17 or newer
• a project layout the compiler can resolve

Basic form:

java -jar cg-language-server.jar <command> [options] <path>

Global commands

simulate

Run the bytecode simulator on a .cg file:

java -jar cg-language-server.jar simulate src/com/example/Counter_test.cg

Common options:

Behavior notes:

• The tool attempts to pick a top-level test entity when --entity is omitted.
• Simulation usually writes a VCD file by default.
• Simulation stops when the test property terminates or when the tool's cycle cap is reached.

Typical uses:

java -jar cg-language-server.jar sim src/com/example/Counter_test.cg
java -jar cg-language-server.jar simulate src/com/example/Counter_test.cg --entity Counter_test

generate

Generate HDL from a source file or project path:

java -jar cg-language-server.jar generate src/com/example/Counter.cg

Common options:

Defaults:

• target: verilog
• output parent: project root (so HDL lands in <projectRoot>/verilog-gen/ or <projectRoot>/vhdl-gen/)

The generator always emits into a verilog-gen/ or vhdl-gen/ subdirectory; --output overrides the parent of that subdirectory, not the subdirectory name itself.

Examples:

java -jar cg-language-server.jar generate src/com/example/Counter.cg
java -jar cg-language-server.jar generate src/com/example/Counter.cg --target vhdl
# Files land at build/hdl/verilog-gen/com/example/...
java -jar cg-language-server.jar generate src --target verilog --output build/hdl

generate-ir

Generate backend IR for inspection or downstream tooling:

java -jar cg-language-server.jar generate-ir src

Common behavior:

• IR is written under .ir/ by default
• inline tasks are emitted as separate IR artifacts

Exit and output expectations

• diagnostics are printed on failure
• generated file paths are reported by the tool or can be inferred from the package structure and output directory
• simulation output includes print(...) statements and runtime errors

Common workflows

End-to-end local loop:

java -jar cg-language-server.jar simulate src/com/example/Counter_test.cg
java -jar cg-language-server.jar generate src/com/example/Counter.cg --target verilog

Explicit entity selection:

java -jar cg-language-server.jar simulate src/com/example/Top.cg --entity Top_test

Project-wide HDL generation:

java -jar cg-language-server.jar generate src --target verilog --output build/verilog

When to pass explicit options

Prefer explicit flags when:

• a file contains multiple candidate top-level entities
• CI needs deterministic output locations
• you generate both Verilog and VHDL in the same project
• several developers share the same repository conventions

Related pages

• Install
• Project layout
• Language server
• Bytecode simulator