Visualize your design

Two views in VS Code draw the design you are editing. The FSM View renders a task as a state machine. The Graph View renders a network as instances wired through ports.

Both read the compiled design - the same intermediate representation the Verilog backend walks. The states and the connections you see are the ones that end up in the generated HDL. Nothing here is guessed from the source text.

Open the views

The views live in the Neosyn panel at the bottom of the window. Click the Neosyn icon in the panel to reveal the FSM View and Graph View tabs.

You can also summon them directly:

• Command Palette (Ctrl/Cmd+Shift+P) → Show FSM View or Show Graph View.
• The two icons on the editor title bar when a .cg file is open.
• Right-click in a .cg editor → Neosyn → Tools.

Each view follows the active editor. Open the .cg file you want to inspect, and the view compiles it and redraws.

FSM View - a task's states

The FSM View shows one task's state machine: every state, and every transition between states. Click a state to jump to the source statements that run in it.

The states come from the compiler, not from counting fences in your text. A task that reads like a single loop() can show several states, because the compiler splits a multi-cycle body into one state per cycle. The count you see is the real one - the same states the generated Verilog uses.

If a file defines more than one task, pick the task you want from the view's selector.

Graph View - a network's wiring

The Graph View shows a network. Each instance is a box. Each port carries its bit width and its interface qualifier - bare, push, stream, or confirm. Every connection between instances is drawn as an edge.

The network's own boundary ports appear at the edges: inputs on the left, outputs on the right. A nested network is marked as such, so you can see where the hierarchy folds. Click any box to jump to its instantiation in the source.

For the Sobel filter example, the view shows the pixels input feeding a line buffer, three shift rows fanning into the kernel instance across its nine p00–p22 ports, and the res output - the exact wiring the Verilog backend emits.

Keep the views in sync

Edits recompile automatically, a short moment after you stop typing. To force a redraw - for example after changing a file the current design imports - run Refresh Views from the panel title bar or the Command Palette.

A view can only draw what compiles. If the active file has errors, fix them and the view redraws on the next successful compile.

Related

• Networks - how instances and ports define the graph the Graph View draws.
• Declarations → Ports - the bare / push / stream / confirm qualifiers shown on each edge.
• Language server - the neosyn/getFsm and neosyn/getGraph methods that back these views.